Experiment A1-1 Italian (Italy) Scrivi i numeri da 0 a 9 nella seguente tabella: 0 1 2 3 4 5 6 7 8 9 Parte A: Dimensionamento del circuito (2.5 punti) A.1 (0.2 pt)
Vout =
A.2 (0.5 pt)
RT1 RT2 RT3 R σR
Experiment A1-2 Italian (Italy) A.3 (0.3 pt) Dimostrazione: A.4 (0.4 pt)
R□=
ρCarbon film = A.5 (0.5 pt) Dimostrazione: Valori misurati: R1 = R2 = κ=
Experiment A1-3 Italian (Italy) A.6 (0.3 pt) Punti R1 Rx Ry Punti R2 Rx Ry Z Z A H B I C J D K E L F M G N V W A.7 (0.3 pt) Punti Punti A H B I C J D K E L F M G N V W
Experiment A1-4 Italian (Italy) Parte B: Curve Caratteristiche del transistor JFET (4.5 punti) B.1 (0.2 pt) IDS = B.2 (0.8 pt) IDS valori della corrente: Base/Collettore (Gate/Drain) Z H I J K L M N W Z A B C D E F G V B.3 (0.2 pt)
f=
Experiment A1-5 Italian (Italy) B.4 (1.2 pt) Usa le colonne vuote per inserire i fattori di correzione che ritieni necessari. Gate A: VGS = RDS = Punti del Collettore/Drain Vout VL out VDS IDS Gate B: VGS = RDS = Punti del Collettore/Drain Vout VL out VDS IDS
Experiment A1-6 Italian (Italy) B.4 (cont.) Gate C: VGS = RDS = Drain point Vout VL out VDS IDS Gate D: VGS = RDS = Drain point Vout VL out VDS IDS
Experiment A1-7 Italian (Italy) B.4 (cont.) Gate E: VGS = RDS = Drain point Vout VL out VDS IDS Base/Gate F: VGS = RDS = Punti del Collettore/Drain Vout VL out VDS IDS
Experiment A1-8 Italian (Italy) B.4 (cont.) Base/Gate G: VGS = RDS = Punti del Collettore/Drain Vout VL out VDS IDS Base/Gate V: VGS = RDS = Punti del Collettore/Drain Vout VL out VDS IDS
Experiment A1-9 Italian (Italy) B.5 (0.5 pt) Curve di output:
Experiment A1-10 Italian (Italy) B.6 (0.5 pt) VGS RDS Grafico: RDS(VGS)
Experiment A1-11 Italian (Italy) B.7 (0.3 pt) Curva di trasferimento: B.8 (0.4 pt) IDSS = VP = B.9 (0.4 pt) Transconduttanza misurata: g= Transconduttanza calcolata dal modello JFET: g=
Experiment A1-12 Italian (Italy) Parte C: Il Transistor a strato sottile di carta (2.0 punti) C.1 (0.8 pt)
Iclosed =
t I t I
Experiment A1-13 Italian (Italy) C.2 (1.2 pt) Grafico: IDS(t) Grafico ulteriore per determinare τ1: τ1 =
Experiment A1-14 Italian (Italy) Parte D: Circuito Inverter (1.0 punto) D.1 (0.5 pt) RL = t Vin Vout
Experiment A1-15 Italian (Italy) D.2 (0.5 pt) Grafico: Vout(Vin)
Topic: Circuits, Electromagnetism, Electrostatics Metodi: Kirchhoff’s Laws, Equivalent Circuit Reduction, Experimental Data Analysis Competenze: Experimental Data Analysis, Graph Linearization, Measurement & Instrumentation Objects: Resistor Fonte: Testo (PDF) — p.1
Experiment A1-1 Italian (Italy) Write the numbers from 0 to 9 in the following table: 0 1 2 3 4 5 6 7 8 9
Part A: Circuit Sizing (2.5 points) A.1 (0.2 pt) Vout =
A.2 (0.5 pt)
RT1 RT2 RT3 R σR
Experiment A1-2 Italian (Italy) A.3 (0.3 pt) Proof:
A.4 (0.4 pt) R□ = ρCarbon film =
A.5 (0.5 pt) Proof: Measured values: R1 = R2 = κ =
Experiment A1-3 Italian (Italy) A.6 (0.3 pt) Points R1 Rx Ry Points R2 Rx Ry Z Z A H B I C J D K E L F M G N V W
A.7 (0.3 pt) Points Points A H B I C J D K E L F M G N V W
Experiment A1-4 Italian (Italy) Part B: JFET Transistor Characteristic Curves (4.5 points) B.1 (0.2 pt) IDS =
B.2 (0.8 pt) IDS values of current: Base/Collector (Gate/Drain) Z H I J K L M N W Z A B C D E F G V
B.3 (0.2 pt) f =
Experiment A1-5 Italian (Italy) B.4 (1.2 pt) Use the empty columns to insert correction factors you consider necessary. Gate A: VGS = RDS = Collector/Drain points Vout VL out VDS IDS
Gate B: VGS = RDS = Collector/Drain points Vout VL out VDS IDS
Experiment A1-6 Italian (Italy) B.4 (cont.) Gate C: VGS = RDS = Drain point Vout VL out VDS IDS
Gate D: VGS = RDS = Drain point Vout VL out VDS IDS
Experiment A1-7 Italian (Italy) B.4 (cont.) Gate E: VGS = RDS = Drain point Vout VL out VDS IDS
Base/Gate F: VGS = RDS = Collector/Drain points Vout VL out VDS IDS
Experiment A1-8 Italian (Italy) B.4 (cont.) Gate/Base G: VGS = RDS = Drain/Collector Points Vout VL out VDS IDS Gate/Base V: VGS = RDS = Drain/Collector Points Vout VL out VDS IDS
Experiment A1-9 Italian (Italy) B.5 (0.5 pt) Output curves:
Experiment A1-10 Italian (Italy) B.6 (0.5 pt) VGS RDS Graph: RDS(VGS)
Experiment A1-11 Italian (Italy) B.7 (0.3 pt) Transfer curve: B.8 (0.4 pt) IDSS = VP = B.9 (0.4 pt) Measured transconductance: g = Transconductance calculated from JFET model: g =
Experiment A1-12 Italian (Italy) Part C: The Thin-Film Transistor on Paper (2.0 points) C.1 (0.8 pt)
Iclosed =
t I t I
Experiment A1-13 Italian (Italy) C.2 (1.2 pt) Graph: IDS(t) Additional graph to determine τ1: τ1 =
Experiment A1-14 Italian (Italy) Part D: Inverter Circuit (1.0 point) D.1 (0.5 pt) RL = t Vin Vout
Experiment A1-15 Italian (Italy) D.2 (0.5 pt) Graph: Vout(Vin)